Why stainless resists rust, why carbon steel earned its reputation for strength, and how modern powder steels like Elmax and MagnaCut collapsed the old trade-off, with a look at the steels Leatherman, Opinel, Victorinox, and Fallkniven actually use.
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E-Shape Open Chord Variations
Every common variation on the open E chord -- sus4, minor, sevenths, sixth, add9 -- each one a single change from the base shape, with fingering and intervals side by side, and a note on how this shape becomes the movable E-shape barre chord.
read moreD-Shape Open Chord Variations
Every common variation on the open D chord -- sus2, sus4, minor, sevenths, sixth, add9 -- each one a single change from the base shape, with fingering and intervals shown side by side.
read moreA-Shape Open Chord Variations
Every common variation on the open A chord -- sus2, sus4, minor, sevenths, sixth, add9 -- each one a single change from the base shape, with fingering and intervals shown side by side.
read moreSupports that peel off: a Bambu Studio profile that stops fighting back
The nine Bambu Studio support settings I change from stock for a 0.4mm nozzle at 0.16mm layer height, and why each one matters when you are trying to get supports off without damaging the part.
read moreDigital Design 03: Metastability
Why a flip-flop can stop between the rails, why two gates reading that voltage can disagree with each other, and why the bug that follows never reproduces.
read moreMulti-tool or separate tools
A Knipex Cobra XS, an Opinel No 08 and a bit driver measured against a Leatherman Wave+ on weight, price and capability.
read moreSoC Intermediate 04: RTL synthesis and timing closure
Why a design can pass sign-off timing and still fail in silicon, and the machinery that decides it: what synthesis optimises, what static timing analysis actually proves, SDC exceptions and the damage they hide, reading a timing report, RTL versus tool fixes, and multi-corner multi-mode closure.
read moreDigital Design 02: Pull-up and pull-down networks
Why a static CMOS gate is always inverting, how series and parallel transistor networks turn into NAND and NOR, why NOR2 is the slower of the pair, and where the extra two transistors in an AND gate go.
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