RockPaperScissors

LizardSpock

Verilog: Timeout

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To wait for a maximum of 10ns for positive edge on clk then carry on with simulation.

fork : wait_or_timeout
  begin
    #10ms;
    disable wait_or_timeout;
  end
  begin
    @(posedge clk);
    disable wait_or_timeout;
  end
join

Often use to fail simulation if the expected signal does not occur, this stops simulation hanging and allows status reports to be generated.

Originally posted as SO answer.

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