APB / Overview

A simple two-phase peripheral bus

APB is the low-power, low-bandwidth member of AMBA — built for register and peripheral access. Every transfer is just two phases: a one-cycle SETUP, then an ACCESS phase the completer can stretch with wait states. No bursts, no pipelining. Open Transfer to step a read and a write through.

The two-phase transfer

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The three operating states

APB / Transfer

Step a transfer, watch the state

Step through a transfer with ◀ ▶. The waveform and the state machine move together — or click any state node to jump there. Start with Write (it has a wait state), then try a back-to-back pair and an error.

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◀

▶

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                state machine
                click a node to jump
              

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APB / State Machine

IDLE · SETUP · ACCESS

Three states, driven entirely by PSEL and PENABLE. From ACCESS, the completer's PREADY decides the exit: stay (wait state), loop to a new SETUP (back-to-back), or return to IDLE. Click a state to inspect it.

Node values — SEL=PSEL · EN=PENABLE  (1=HIGH, 0=LOW)

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APB / Signal Reference

Signals & state table

REQ→CMP = driven by the requester (bridge), CMP→REQ = driven by the completer (peripheral).

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State table

              StatePSELPENABLEMeaning
            

SETUP always lasts exactly one cycle. ACCESS holds until PREADY is HIGH; every cycle PREADY is LOW is a wait state. PSLVERR and PRDATA are sampled on the cycle PREADY is HIGH. APB4 adds PSTRB (write byte lanes) and PPROT (protection); APB5 adds wakeup/user signals.