AMBA · Bus Architecture

AMBA Interface Explorer

Interactive, signal-level walkthroughs of the AMBA protocol family. Pick an interface to step through its channels, handshakes and transactions.

4 interfaces · all ready
AXI3 · 4 · 5 Ready
Advanced eXtensible Interface
High-throughput, memory-mapped transport. Five independent channels with bursts, transaction IDs and out-of-order completion.
Channels
AW W B AR R
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ACE4 · 5 Ready
AXI Coherency Extensions
Cache-coherent AXI. Three snoop channels let caching masters share memory in hardware — dirty lines move cache-to-cache, no software flushes.
Snoop channels
AC CR CD + MOESI
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LPI Ready
Low-Power Interface
Handshake-based control for clock and power management — the Q-Channel gates clocks/power, the P-Channel negotiates device power states.
Q-Channel · clock / power gating
QACTIVE QREQn QACCEPTn QDENY
P-Channel · power-state transitions
PREQ PSTATE PACCEPT PDENY PACTIVE
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APB Ready
Advanced Peripheral Bus
A simple, low-power, low-bandwidth interface for register and peripheral access. No bursts — every transfer is a two-phase setup then access.
Transfer phases
IDLE → SETUP → ACCESS
Signals
PSEL PENABLE PADDR PWRITE PREADY
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AXI, ACE, LPI and APB explorers are all live — step through any interface signal by signal.
Network explorers

Move up a level: whole interconnects rather than a single interface — multiple masters, slaves and controllers negotiating together.

AXI Network Masters, interconnect and slaves — routing, IDs and ordering across a fabric. Explore → APB Network A bridge and its peripheral subsystem — decode, select and wait states. Explore → LPI Network A PCK-600 power controller driving Q- and P-Channels across a whole SoC. Explore →