Basics / Overview

Five independent channels

AXI splits every memory transaction across five one-way channels. Writes use three (AW, W, B); reads use two (AR, R). Each channel is fully independent and uses the same VALID/READY handshake. Hover any channel to highlight it across the diagram, or click a card below to open its walkthrough.

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One rule governs every channel

A transfer happens on a rising clock edge only when both VALID and READY are high. The source raises VALID; the destination raises READY. Neither may wait on the other to assert first. Walk through it in Handshake →

Basics / Handshake

The VALID / READY handshake

Every channel transfers information the same way. The source asserts VALID when its payload is valid; the destination asserts READY when it can accept. Pick a scenario, then step the clock.

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no deadlock rule

A source must not wait for READY before asserting VALID. Once VALID is high it must stay high until the transfer completes.

destination freedom

A destination may assert READY before VALID, or wait — and can drop READY between transfers to apply backpressure.

Transactions / Write

Anatomy of a write

A write moves across three channels: address on AW, a burst of data beats on W (last beat flagged by WLAST), then a single response on B. Step the clock and hover any signal to inspect it.

              
              write_burst.vcd — 2 beats

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Transactions / Read

Anatomy of a read

A read uses two channels: the manager requests an address on AR, then the subordinate returns data beats on R. The read response (RRESP) rides with each beat; RLAST marks the end of the burst.

              
              read_burst.vcd — 2 beats

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Transactions / Bursts

Burst types & addressing

One address phase can transfer many beats. AxBURST sets how the address advances; AxLEN the beat count; AxSIZE the bytes per beat. Adjust the controls to see the addresses each beat lands on.

AxBURST

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AxLEN · beats

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AxSIZE · bytes/beat

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Transactions / IDs & Ordering

Transaction IDs & out-of-order

Each transaction carries an ID (AxID). Transactions with different IDs have no ordering guarantee — a subordinate may return them in any order, enabling pipelining. Same-ID transactions must stay ordered. Step through two outstanding reads returning out of order.

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different IDs → reorderable

ID=2 was issued after ID=1 but returns first. Legal, because their IDs differ — the manager matches responses by RID.

same ID → in order

Two reads sharing an ID must return in issue order. Interleaving of read data beats across different IDs is also disallowed in AXI4.

Sidebands / Exclusive Access

Exclusive access & the lock signals

AXI implements atomic read-modify-write without bus locking. A manager does an exclusive read (ARLOCK) then an exclusive write (AWLOCK) to the same location. A monitor in the subordinate decides whether the write is allowed — signalled back as EXOKAY or OKAY on BRESP.

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              exclusive_access.vcd — read 0x40 → write 0x40

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Version note: AXI3 AxLOCK is 2-bit — Normal / Exclusive / Locked / —. AXI4 dropped Locked and narrowed AxLOCK to 1-bit (Exclusive only). Exclusive monitors have an implementation-defined limit on outstanding exclusive sequences and the addressable region.

Sidebands / Qualifiers

Transaction qualifiers

Beyond address and data, every request carries attribute sidebands that describe how it should be treated — its permissions, cacheability, priority and routing. They ride the AW / AR address channels under the existing VALID/READY handshake — no handshake of their own — and stay constant for the whole transaction.

AxPROT [2:0] M {{ protDir.arrowEl }} S since AXI3

Three independent access attributes. The subordinate or interconnect uses them for permission checks — they never alter the data path.

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AxCACHE [3:0] M {{ cacheDir.arrowEl }} S since AXI3

Four bits that classify the target memory and how the system may optimise the access.

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Common ARCACHE encodings

AWCACHE uses the same four bits, but the allocate pair [3:2] swaps role — bit 3 is Write-Allocate and bit 2 is the read-side hint. Codes 0000–0011 are identical on read and write.

AxQOS [3:0] M {{ qosDir.arrowEl }} S AXI4+

A 4-bit priority hint. 0b0000 is the default (no QoS); higher values request higher priority. It is purely an arbitration hint to the interconnect — it never affects ordering or correctness. AW and AR carry independent values.

AxREGION [3:0] M {{ regionDir.arrowEl }} S AXI4+

A 4-bit region identifier. It lets one physical subordinate port present up to 16 separate address regions, so the interconnect needn't re-decode inside the slave. Driven from the address map during decode; constant for the transaction.

xUSER impl-defined width AWUSER · WUSER · BUSER · ARUSER · RUSER AXI4+

Optional user-defined sidebands on every channel — direction follows the channel (M→S on AW/AR/W, S→M on R/B). The protocol never interprets them; they must be carried end-to-end unchanged. Because their meaning is agreed privately between two components, xUSER is an interoperability hazard — mixing IP that disagrees on its definition silently breaks.

Reference / Versions

AXI3 → AXI4 → AXI5

The five channels and the VALID/READY handshake are unchanged since 2003 — what evolved is the sideband signals. AXI4 reshaped control and dropped interleaving; AXI5 layered on optional resilience and scalability. Select a version to spotlight its column.

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Signal

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What changed

Carried from AXI3 — later changed

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Introduced in AXI4

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Introduced in AXI5 · tagged by issue — AXI5 began at IHI 0022 Issue F; each row shows the issue that added it

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AXI5 issue timeline

AXI5 features are optional and backward-compatible — an AXI4 interface interoperates by tying off the new sidebands. Issue letters skip I (H → J). Prefixes: Ax = AW & AR, x = all relevant channels.

Reference / Variants

AXI vs AXI-Lite vs AXI-Stream

Three members of the AXI family for three jobs: full AXI for high-throughput memory, AXI-Lite for simple register access, AXI-Stream for point-to-point data flow with no addresses at all.

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Reference / Cheat Sheet

Signal reference

The core signals on each channel. M→S = driven by manager, S→M = driven by subordinate. Suffixed buses (AxID, AxLEN …) share the channel's handshake.

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