The infrastructure that makes a SoC run correctly and efficiently: PLLs for frequency synthesis, clock trees for low-skew distribution, clock domain crossings and metastability, reset sources and synchronisation, and power domains with gating and DVFS.
read moreOther articles
SoC Article 06: Interconnects and Bus Protocols - AXI, AHB, and APB
How SoC blocks communicate: the AMBA bus family from simple APB peripherals through pipelined AHB to the high-performance AXI4 with its five independent channels, valid/ready handshake, and crossbar interconnects.
read moreSoC Article 05: Memory Architecture - Caches, DRAM, and On-chip Storage
How modern SoCs bridge the speed gap between fast CPU cores and slow external DRAM through cache hierarchies, SRAM, and DRAM controllers. Covers cache organisation, MESI coherency, the MMU, and on-chip storage.
read moreSoC Article 04: Processor Cores - CPU, DSP, GPU and Hardware Accelerators
A survey of the main processor types in modern SoCs: CPUs for general-purpose code, DSPs for signal processing, GPUs for parallel workloads, and hardware accelerators for AI, video, and cryptography.
read moreSoC Article 03: The SoC Design Stack - From Transistors to Software
How SoC design is organised as a stack of abstraction layers, from transistors at the bottom to application software at the top, and the languages and tools used at each level.
read moreSoC Article 02: What is a System on Chip? - Anatomy and Motivation
What blocks make up a System on Chip, how do they relate, and why does integration deliver such dramatic benefits over traditional board-level designs?
read moreSoC Article 01: From Room to Silicon — The Story of the Computer System
How computing evolved from room-filling mainframes to a sliver of silicon in your pocket — and why that history shapes modern SoC design.
read moreWaveDrom Timing Diagrams in Pelican with Claude Code
"flip-flop"
A flip-flop (D-Type) is essentially 2 latches in series with the enable to one inverted. This stops the flip-flop from …
read more