I've been using Claude Code for RTL generation lately, and the missing piece was a tight feedback loop between code …
read moreOther articles
"SystemVerilog: RTL Types"
read moreregandwirewere the original synthesisable types. Wires are constantly assigned and regs are evaluated at particular points, the …"SystemVerilog: Constrained Random"
A minimal example of constrained random to constraining a 4 bit value to 0 to 11 when randomised.
read moremodule tb …"git submodule update fatal"
$ git submodule update fatal: Needed a single revision Unable to find current revision in submodule path 'vim/bundle/systemverilog'To …
read more"flip-flop"
A flip-flop (D-Type) is essentially 2 latches in series with the enable to one inverted. This stops the flip-flop from …
read moreTasks Using Absolute Delays
As previously mentioned SystemVerilog introduced abolute delays in the form of
read more#1s;,#1ms,#1us,#1ns. Using these as values passed …