Basics / Overview

AXI, plus hardware coherency

ACE — the AXI Coherency Extensions — keeps every one of AXI's five channels and adds the machinery to let multiple caching masters share memory without software flushes. It bolts on three new snoop channels, a set of coherency qualifiers on AR/AW, and a five-state MOESI line model.

Inherited from AXI · 5 channels

open AXI explorer →

New in ACE · 3 snoop channels

{{ c.code }} M {{ c.dir.arrowEl }} I

{{ c.cta }} →

§

The address channels grow coherency qualifiers

No new channels for these — they extend the existing AR and AW, so they share their colours:

SNOOP picks the transaction's coherency intent · DOMAIN sets how far it propagates · BAR marks a memory barrier. Walk them in Domains & types →

Basics / Cache Line States

MOESI — five states per cache line

Every coherent cache line sits in one of five states, defined by two questions: is this copy unique (no other cache has it) or shared, and is it clean (matches memory) or dirty? Click a cell to inspect it.

Unique

Shared

Clean

{{ s.tag }}

Dirty

{{ s.tag }}

On a snoop

Channels / Snoop

The three snoop channels

When a coherent access needs to know what other caches hold, the interconnect snoops them. A snoop is one transaction over three channels: address in on AC, a mandatory response out on CR, and — only if data is owed — a line out on CD. Step the clock.

              
              snoop.vcd — interconnect snoops the master

◀

▶

{{ snoopStepLabel }}

            {{ inspLabel }} · {{ inspText }}
          

Transactions / Coherent Read

ReadShared — a snoop that hits dirty data

CPU 0 issues a ReadShared for a line that CPU 1 holds Modified. Watch the dirty line move cache-to-cache — main memory is never touched. Step the clock; signals below the divider belong to the snooped CPU 1.

            line 0x40 state:
            CPU 0{{ cohCpu0 }}
            ·
            CPU 1{{ cohCpu1 }}
          

              
              readshared.vcd — cache-to-cache transfer

◀

▶

{{ cohStepLabel }}

            {{ inspLabel }} · {{ inspText }}
          

Reference / Domains & Types

Shareability domains & snoop types

Two qualifiers on every coherent address-channel beat decide its behaviour: DOMAIN bounds how far the access is kept coherent, and SNOOP picks which coherent transaction it is.

AxDOMAIN · shareability

{{ d.name }}

ARSNOOP · read transactions

AWSNOOP · write transactions

Reference / Versions

ACE across AMBA generations

ACE arrived with AMBA 4 on top of AXI4, then grew in AMBA 5. The Lite variants trade full two-way coherency for a much smaller, one-way footprint.

                    {{ r.k }}
                    {{ r.v }}
                  

Reference / Cheat Sheet

ACE signal cheat sheet

Only the coherency additions are listed — the five AXI channels and their VALID/READY pairs carry over unchanged. M=cached master, I=interconnect.