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1. "Verilog: define if not defined"

   To set a default define option while allowing it to be overridden from the command line.

   `ifndef mode_sel
     `define mode_sel …

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2. "Verilog: shm waveforms"

   The best practice is to use a tcl file:

   shm.tcl

   database -open waves -shm
   probe -create your_top_level -depth all …

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3. "Verilog Timeformat"

   Time can be displayed during simulation using %t.

   $display("%t", $realtime);
   

   Timeformat is used to control the way (%t) this …

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4. "SystemVerilog: Constrained Random"

   A minimal example of constrained random to constraining a 4 bit value to 0 to 11 when randomised.

   module tb …

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5. "Verilog: Thermometer Code"

   Efficiently create a [thermometer code][wiki] in verilog:

   localparam M = 32;
   
   function [M-1:0] therm_code;
     input    [$clog2(M):0 …

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6. "Verilog: Calculate primes"

   Based on my answer to this SO Question.

   Definition of Prime:

   A Prime Number can be divided evenly only by …

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7. "Verilog: Timeout"

   To wait for a maximum of 10ns for positive edge on clk then carry on with simulation.

   fork : wait_or_timeout
     begin …

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8. "Verilog importing envvar"

   Based on a Stackoverflow answer, to import environment variables into Verilog you can use:

   import "DPI-C" function string getenv(input …

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9. "$display without a line return"

   In Verilog to output to stdout without a line return use $write();

   Equivalent statements :

   $write("\n");
   $display("");
   

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10. "Navigate Verilog with VIM"

    Using gf

    In your vimrc

    " gf goto_file, automatically add search for these file extensions
    :set suffixesadd+=.v
    :set suffixesadd+=.sv …

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11. Tasks Using Absolute Delays

    As previously mentioned SystemVerilog introduced abolute delays in the form of #1s;, #1ms, #1us, #1ns. Using these as values passed …

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