Why two threads with separate counters can run slower than one thread, and the coherency machinery that explains it: the single-writer rule, MESI states, read-for-ownership, snooping, directories, snoop filters, and the cache line granularity that no amount of reading the source code reveals.
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SoC Intermediate 01: AXI4 protocol deep dive
The mechanisms behind AXI4 throughput and the bugs each one creates: burst encoding, transaction identifiers, out-of-order completion, outstanding transaction tracking, quality of service signalling, and the handshake rules that hand-written bridges break most often.
read moreSoC Article 10: The SoC design flow - From specification to silicon
A complete walkthrough of the SoC design flow, from specification and architecture through RTL coding, functional verification, synthesis, physical design, and sign-off to tape-out and fabrication.
read moreRequirements Writing
Good requirements engineering is fundamental to delivering products that meet customer needs within cost and schedule. A well-formed requirement identifies …
read more"SystemVerilog: Constrained Random"
A minimal example of constrained random to constraining a 4 bit value to 0 to 11 when randomised.
read moremodule tb …Tasks Using Absolute Delays
As previously mentioned SystemVerilog introduced abolute delays in the form of
read more#1s;,#1ms,#1us,#1ns. Using these as values passed …