Why a flip-flop can stop between the rails, why two gates reading that voltage can disagree with each other, and why the bug that follows never reproduces.
read moreOther articles
SoC Intermediate 04: RTL synthesis and timing closure
Why a design can pass sign-off timing and still fail in silicon, and the machinery that decides it: what synthesis optimises, what static timing analysis actually proves, SDC exceptions and the damage they hide, reading a timing report, RTL versus tool fixes, and multi-corner multi-mode closure.
read moreDigital Design 02: Pull-up and pull-down networks
Why a static CMOS gate is always inverting, how series and parallel transistor networks turn into NAND and NOR, why NOR2 is the slower of the pair, and where the extra two transistors in an AND gate go.
read moreDigital Design 01: Mask sets, and how a transistor gets built
What a photomask is, the sequence of masks that turns a blank wafer into a MOSFET, why the mask count keeps climbing, the approximate cost of a mask set at each geometry from 250 nm down to 3 nm, and what an A1 metal spin costs against a B0 all-layer respin.
read moreSoC Intermediate 03: Pipeline design and hazards
Why adding a pipeline stage can make a processor slower, and the hazard machinery that decides the outcome: forwarding paths, load-use stalls, branch prediction and flush, structural conflicts, multi-cycle units, and the valid bits that keep exceptions precise.
read moreSoC Intermediate 02: Cache coherency protocols
Why two threads with separate counters can run slower than one thread, and the coherency machinery that explains it: the single-writer rule, MESI states, read-for-ownership, snooping, directories, snoop filters, and the cache line granularity that no amount of reading the source code reveals.
read moreSoC Intermediate 01: AXI4 protocol deep dive
The mechanisms behind AXI4 throughput and the bugs each one creates: burst encoding, transaction identifiers, out-of-order completion, outstanding transaction tracking, quality of service signalling, and the handshake rules that hand-written bridges break most often.
read moreSoC Article 11: HW/SW co-design, bridging software and silicon
How hardware and software are designed together on a SoC: the boot process from reset to running OS, device drivers, the HW/SW partitioning decision, virtual platforms, and the RTOS vs Linux choice.
read moreSoC Article 10: The SoC design flow - From specification to silicon
A complete walkthrough of the SoC design flow, from specification and architecture through RTL coding, functional verification, synthesis, physical design, and sign-off to tape-out and fabrication.
read moreAMBA low power interface: Q-Channel and P-Channel explained
A practical guide to AMBA Low Power Interface handshake protocols: Q-Channel and P-Channel signal tables, state machines, timing diagrams, and design rules from ARM IHI0068.
read moreSoC Article 09: Hardware Description Languages and RTL Design
How SoC hardware is described in code: the fundamental difference between sequential software and parallel hardware, RTL vs behavioural vs structural design, SystemVerilog key constructs, FSMs, testbenches, assertions, and the synthesis step that turns RTL into gates.
read moreSoC Article 08: Peripherals and I/O - Connecting the SoC to the world
A survey of the most common peripheral types found in SoCs: GPIO, UART, SPI, I2C, USB, Ethernet, DMA, and interrupt controllers, and how they connect the digital logic inside the chip to the physical world outside it.
read moreSoC Article 07: Clocking, Reset, and Power Domains
The infrastructure that makes a SoC run correctly and efficiently: PLLs for frequency synthesis, clock trees for low-skew distribution, clock domain crossings and metastability, reset sources and synchronisation, and power domains with gating and DVFS.
read moreParametric Knob Maker for OpenSCAD
A fork of aminGhafoory's parametric-knob-maker that adds a generalised round knob module with configurable offset base, chamfers, and grip cutouts. Covers the knob() and hex_knob() modules, the key parameters, and how to combine the result with a BOSL2 screw for a complete thumbscrew assembly.
read moreRFC 2119 Requirements Keywords
RFC 2119 defines a vocabulary of requirement keywords -- MUST, SHOULD, MAY and their negatives -- widely used in IETF specifications and software engineering. This post covers the full RFC 2119 keyword set, the capitalisation convention introduced by RFC 8174, and the key differences from the IEEE normative term conventions covered in the earlier requirements writing post.
read moreSoC Article 06: Interconnects and Bus Protocols - AXI, AHB, and APB
How SoC blocks communicate: the AMBA bus family from simple APB peripherals through pipelined AHB to the high-performance AXI4 with its five independent channels, valid/ready handshake, and crossbar interconnects.
read moreSoC Article 05: Memory Architecture - Caches, DRAM, and On-chip Storage
How modern SoCs bridge the speed gap between fast CPU cores and slow external DRAM through cache hierarchies, SRAM, and DRAM controllers. Covers cache organisation, MESI coherency, the MMU, and on-chip storage.
read moreSoC Article 04: Processor Cores - CPU, DSP, GPU and Hardware Accelerators
A survey of the main processor types in modern SoCs: CPUs for general-purpose code, DSPs for signal processing, GPUs for parallel workloads, and hardware accelerators for AI, video, and cryptography.
read moreSoC Article 03: The SoC design stack, from transistors to software
How SoC design is organised as a stack of abstraction layers, from transistors at the bottom to application software at the top, and the languages and tools used at each level.
read moreSoC Article 02: What is a System on Chip, anatomy and motivation
What blocks make up a System on Chip, how do they relate, and why does integration deliver such dramatic benefits over traditional board-level designs?
read moreEmotional Intelligence in the Workplace
A summary of high and low emotional intelligence (EQ) traits in leaders and employees, and how EQ shapes team dynamics and decision making.
read moreMakerWorld Parametric Models with OpenSCAD
How to create customizable parametric models on MakerWorld using OpenSCAD scripts.
read moreOpenSCAD on Apple Silicon
Installing OpenSCAD on Apple Silicon Macs using Homebrew.
read moreSoC Article 01: From Room to Silicon — The Story of the Computer System
How computing evolved from room-filling mainframes to a sliver of silicon in your pocket, and why that history shapes modern SoC design.
read moreRequirements Writing
Good requirements engineering is fundamental to delivering products that meet customer needs within cost and schedule. A well-formed requirement identifies …
read moreFSM Diagrams in Pelican and Claude Code
Finite state machines turn up everywhere: protocol implementations, hardware controllers, UI flows, parsers. Drawing them well is useful but tedious …
read moreVerilog Lint Skill for Claude Code
I've been using Claude Code for RTL generation lately, and the missing piece was a tight feedback loop between code …
read moreWaveDrom Timing Diagrams in Pelican with Claude Code
Adaptive Filter Theory Notes 1
Notes From Reading Adaptive Signal Theory (5th Ed) by Simon Haykin
Three Basic Kinds Of Estimation
- Filtering - Extraction of Current …
"Matlab: floating point checking equality"
As previously decribed floating point arithmetic is not associative. Which means it is very easy for floating point models not …
read more"Matlab: linear progressions"
"Matlab: functions inputs parsed based on outputs"
It is quite common to detect how many input arguments have been passed to a function, using
read morenargin(N arguments …"SystemVerilog: RTL Types"
read moreregandwirewere the original synthesisable types. Wires are constantly assigned and regs are evaluated at particular points, the …"Verilog: define if not defined"
To set a default define option while allowing it to be overridden from the command line.
read more`ifndef mode_sel `define mode_sel …"Verilog: shm waveforms"
The best practice is to use a tcl file:
shm.tcl
read moredatabase -open waves -shm probe -create your_top_level -depth all …"Verilog Timeformat"
Time can be displayed during simulation using
%t.$display("%t", $realtime);Timeformat is used to control the way (
read more%t) this …"SystemVerilog: Constrained Random"
A minimal example of constrained random to constraining a 4 bit value to 0 to 11 when randomised.
read moremodule tb …"Verilog: Thermometer Code"
Efficiently create a [thermometer code][wiki] in verilog:
read morelocalparam M = 32; function [M-1:0] therm_code; input [$clog2(M):0 …"Verilog: Calculate primes"
"Submit to SGE as if working locally"
Setting an alias in you .tcshrc
alias qrun 'qrsh -V -noshell -cwd !*'or bash
read morealias qrun='qrsh -V -noshell -cwd …"Simulink: Scroll wheel erratic behaviour"
On Mac OS X matlab behaves quite oddly with the track pad zooming in and out very quickly and erratically …
read more"Matlab editor no tabs"
Matlab always use to open text files in tabs in the same editor window. When switching to 2014a documents started …
read more"Simulink: Globally set sample time"
To set each constant in a model to sample time -1:
read moreblks = find_system(dut, 'BlockType', 'Constant'); for i = 1:length …"Simulink: list programmable block properties"
Select a block ie gain in Simulink then in Matlab type:
get(gcbh)This shows the list of properties which …
read more"Matlab: Find all gain blocks"
find_system('BlockType', 'Gain')This will list all gain blocks in currently loaded models. to limit to a particulat model:
read morefind_system …"Floating Point Arithmetic is not Associative"
"Verilog: Timeout"
To wait for a maximum of
10nsfor positive edge on clk then carry on with simulation.read morefork : wait_or_timeout begin …"Matlab Remove Elements from Array"
"Matlab: Formatting Strings"
"Matlab: Grid"
To add X and Y grids to plots :
grid on;
To add Y only grid:
read moreset(gca,'XGrid','off','YGrid …"Matlab: Line Breaks in Strings"
Wrap strings with
sprintfto allow the\nto be escaped correctly.read more>> disp('hello\nworld') hello\nworld >> disp(sprintf('hello …"Matlab: Listing field name values of a struct"
"Matlab toolboxes with absolute path setup"
When a script or function is called with
read morerun(./relative/path/script)the working directory is changed to the./relative …"Matlab: Array content check"
Checking if an Array contains a number:
input = [1,2,3,4]; check = 4; any(input==4)Check if a …
read more"Matlab: Split Odd & Even Array Elements"
Using Matlab to splitting data into odd and even samples.
A for loop approach:
read moredata_odd = []; data_even = []; for i = 1:length …"Verilog importing envvar"
Based on a Stackoverflow answer, to import environment variables into Verilog you can use:
read moreimport "DPI-C" function string getenv(input …"Matlab: leading 0's"
For adding leading zeros to a number the following can be used for 4 decimal places with integer input:
read moredat …"Matlab Wrapper Scripts"
To wrap a function with variable input arguments and pass them all on to the wrapped function. Based on a …
read more"Matlab sort_by"
In ruby we can perform schwartzian transforms easily with the sort_by method. This allows sorting enumerators by any property.
For …
read more"Beyond the LSB"
If we truncate a number, that is to throw away the LSBs (least significant bits) we loose resolution.
A 4 …
read more"Matlab Function Outputs"
Handling functions with extraneous leading outputs. For example:
read morefunction [a,b] = dummy_function a = 10; b = 20; endfunction [a, b] = dummy_function …"Matlab Shuffle Array"
To shuffle a:
a(randperm(length(a)))Example:
read morea = [10 2 5 20]; a = a(randperm(length(a))) a = 5 …"OO Magic Bullet?"
I do not think that there are any magic bullets, best practises can minimise risk but you have to fully …
read more"$display without a line return"
In Verilog to output to stdout without a line return use
$write();Equivalent statements :
read more$write("\n"); $display("");"Object-Oriented Matlab"
Mathworks Article on Object-Oriented programming for Matlab.
A quick example of the syntax:
read moreclassdef sads properties Name SampleRate end properties …"Matlab: legend colours"
When plotting several lines in Matlab, I have become aware of how hard it was to see the colours in …
read more"Matlab benchmarking"
In the following example we test the allocation speed of different types:
read moresamples_to_avg = 10000; for i=1:samples_to_avg tic; t …"Matlab remove values from array"
"flip-flop"
A flip-flop (D-Type) is essentially 2 latches in series with the enable to one inverted. This stops the flip-flop from …
read more"Matlab repeat a matrix n times"
repmat(matrix, [repeat_y, repeat_x])
Horizontal
read morerepmat([1 2 3],[1,4]) ans = 1 2 3 1 2 3 1 2 …"Matlab setting Simulink simulation stop time"
Running the Simulink model model.mdl from matlab for a specified time:
sim('model', stoptime)Where stoptime is a number …
read more"Name Spacing in Matlab"
A typical work flow in Matlab involves a folder filled with scripts and functions. Over time this folder grows until …
read more"Navigate Verilog with VIM"
Using
gfIn your vimrc
read more" gf goto_file, automatically add search for these file extensions :set suffixesadd+=.v :set suffixesadd+=.sv …"Testing Matlab Arrays for Equality."
Testing a matlab array for equality can be doen a few different was some have surprising side effects if your …
read more"Device Ownership Password"
While using a pool laptop from work and trying to connect to my home wifi I am prompted for my …
read more"iPad 3 Tethering"
Three now have tethering available for the iPad 3, which can be read in the comments by moderators on the …
read moreTasks Using Absolute Delays
As previously mentioned SystemVerilog introduced abolute delays in the form of
read more#1s;,#1ms,#1us,#1ns. Using these as values passed …"Matlab Scripting Axes Properties"
Matlab figure properties which can be set through the properties editor can also be set by scripts. My main stumbling …
read more