Why a bus can cross a clock domain through correct synchronisers and still deliver a value that never existed, and the structures that prevent it: metastability and the two-flop MTBF, toggle synchronisers, handshakes, Gray-coded pointers, asynchronous FIFOs, reset crossings, and reconvergence.
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SoC Intermediate 04: RTL synthesis and timing closure
Why a design can pass sign-off timing and still fail in silicon, and the machinery that decides it: what synthesis optimises, what static timing analysis actually proves, SDC exceptions and the damage they hide, reading a timing report, RTL versus tool fixes, and multi-corner multi-mode closure.
read moreSoC Intermediate 03: Pipeline design and hazards
Why adding a pipeline stage can make a processor slower, and the hazard machinery that decides the outcome: forwarding paths, load-use stalls, branch prediction and flush, structural conflicts, multi-cycle units, and the valid bits that keep exceptions precise.
read moreSoC Intermediate 02: Cache coherency protocols
Why two threads with separate counters can run slower than one thread, and the coherency machinery that explains it: the single-writer rule, MESI states, read-for-ownership, snooping, directories, snoop filters, and the cache line granularity that no amount of reading the source code reveals.
read moreSoC Intermediate 01: AXI4 protocol deep dive
The mechanisms behind AXI4 throughput and the bugs each one creates: burst encoding, transaction identifiers, out-of-order completion, outstanding transaction tracking, quality of service signalling, and the handshake rules that hand-written bridges break most often.
read moreSoC Article 11: HW/SW co-design, bridging software and silicon
How hardware and software are designed together on a SoC: the boot process from reset to running OS, device drivers, the HW/SW partitioning decision, virtual platforms, and the RTOS vs Linux choice.
read moreSoC Article 10: The SoC design flow - From specification to silicon
A complete walkthrough of the SoC design flow, from specification and architecture through RTL coding, functional verification, synthesis, physical design, and sign-off to tape-out and fabrication.
read moreAMBA low power interface: Q-Channel and P-Channel explained
A practical guide to AMBA Low Power Interface handshake protocols: Q-Channel and P-Channel signal tables, state machines, timing diagrams, and design rules from ARM IHI0068.
read moreSoC Article 09: Hardware Description Languages and RTL Design
How SoC hardware is described in code: the fundamental difference between sequential software and parallel hardware, RTL vs behavioural vs structural design, SystemVerilog key constructs, FSMs, testbenches, assertions, and the synthesis step that turns RTL into gates.
read moreSoC Article 08: Peripherals and I/O - Connecting the SoC to the world
A survey of the most common peripheral types found in SoCs: GPIO, UART, SPI, I2C, USB, Ethernet, DMA, and interrupt controllers, and how they connect the digital logic inside the chip to the physical world outside it.
read moreSoC Article 07: Clocking, Reset, and Power Domains
The infrastructure that makes a SoC run correctly and efficiently: PLLs for frequency synthesis, clock trees for low-skew distribution, clock domain crossings and metastability, reset sources and synchronisation, and power domains with gating and DVFS.
read moreSoC Article 06: Interconnects and Bus Protocols - AXI, AHB, and APB
How SoC blocks communicate: the AMBA bus family from simple APB peripherals through pipelined AHB to the high-performance AXI4 with its five independent channels, valid/ready handshake, and crossbar interconnects.
read moreSoC Article 05: Memory Architecture - Caches, DRAM, and On-chip Storage
How modern SoCs bridge the speed gap between fast CPU cores and slow external DRAM through cache hierarchies, SRAM, and DRAM controllers. Covers cache organisation, MESI coherency, the MMU, and on-chip storage.
read moreSoC Article 04: Processor Cores - CPU, DSP, GPU and Hardware Accelerators
A survey of the main processor types in modern SoCs: CPUs for general-purpose code, DSPs for signal processing, GPUs for parallel workloads, and hardware accelerators for AI, video, and cryptography.
read moreSoC Article 03: The SoC design stack, from transistors to software
How SoC design is organised as a stack of abstraction layers, from transistors at the bottom to application software at the top, and the languages and tools used at each level.
read moreSoC Article 02: What is a System on Chip, anatomy and motivation
What blocks make up a System on Chip, how do they relate, and why does integration deliver such dramatic benefits over traditional board-level designs?
read moreSoC Article 01: From Room to Silicon — The Story of the Computer System
How computing evolved from room-filling mainframes to a sliver of silicon in your pocket, and why that history shapes modern SoC design.
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