Why a design can pass sign-off timing and still fail in silicon, and the machinery that decides it: what synthesis optimises, what static timing analysis actually proves, SDC exceptions and the damage they hide, reading a timing report, RTL versus tool fixes, and multi-corner multi-mode closure.
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SoC Intermediate 03: Pipeline design and hazards
Why adding a pipeline stage can make a processor slower, and the hazard machinery that decides the outcome: forwarding paths, load-use stalls, branch prediction and flush, structural conflicts, multi-cycle units, and the valid bits that keep exceptions precise.
read moreUsing ctags with Verilog and SystemVerilog
How to generate and use ctags for Verilog/SystemVerilog projects, covering design.vc file lists, editor setup for Vim, Neovim, Emacs, and VS Code, and keeping tags up to date automatically.
read moreSoC Article 10: The SoC design flow - From specification to silicon
A complete walkthrough of the SoC design flow, from specification and architecture through RTL coding, functional verification, synthesis, physical design, and sign-off to tape-out and fabrication.
read moreSoC Article 09: Hardware Description Languages and RTL Design
How SoC hardware is described in code: the fundamental difference between sequential software and parallel hardware, RTL vs behavioural vs structural design, SystemVerilog key constructs, FSMs, testbenches, assertions, and the synthesis step that turns RTL into gates.
read moreSoC Article 03: The SoC design stack, from transistors to software
How SoC design is organised as a stack of abstraction layers, from transistors at the bottom to application software at the top, and the languages and tools used at each level.
read moreFSM Diagrams in Pelican and Claude Code
Finite state machines turn up everywhere: protocol implementations, hardware controllers, UI flows, parsers. Drawing them well is useful but tedious …
read moreVerilog Lint Skill for Claude Code
I've been using Claude Code for RTL generation lately, and the missing piece was a tight feedback loop between code …
read moreWaveDrom Timing Diagrams in Pelican with Claude Code
"SystemVerilog: RTL Types"
read moreregandwirewere the original synthesisable types. Wires are constantly assigned and regs are evaluated at particular points, the …"flip-flop"
A flip-flop (D-Type) is essentially 2 latches in series with the enable to one inverted. This stops the flip-flop from …
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