Other articles

1. SoC Article 09: Hardware Description Languages and RTL Design

   How SoC hardware is described in code: the fundamental difference between sequential software and parallel hardware, RTL vs behavioural vs structural design, SystemVerilog key constructs, FSMs, testbenches, assertions, and the synthesis step that turns RTL into gates.

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2. SoC Article 03: The SoC design stack, from transistors to software

   How SoC design is organised as a stack of abstraction layers, from transistors at the bottom to application software at the top, and the languages and tools used at each level.

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3. FSM Diagrams in Pelican and Claude Code

   Finite state machines turn up everywhere: protocol implementations, hardware controllers, UI flows, parsers. Drawing them well is useful but tedious …

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4. Verilog Lint Skill for Claude Code

   I've been using Claude Code for RTL generation lately, and the missing piece was a tight feedback loop between code …

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5. WaveDrom Timing Diagrams in Pelican with Claude Code

   WaveDrom is a JavaScript library that renders digital timing diagrams from a simple JSON-based format called WaveJSON. It's widely used …

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6. "SystemVerilog: RTL Types"

   reg and wire were the original synthesisable types. Wires are constantly assigned and regs are evaluated at particular points, the …

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7. "flip-flop"

   A flip-flop (D-Type) is essentially 2 latches in series with the enable to one inverted. This stops the flip-flop from …

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